What is clock mixing in DFT?
Majorly, in DFT, we avoid mixing different clocks in the same chain, but if there is a constraint to I/O ports we have to stitch scan flops driven by two different clocks in one chain.
What is lock up latch?
A lock-up latch is a transparent latch used to avoid large clock skew and mitigate the problem in closing hold timing due to large uncommon clock path.
Can we convert latch to scan cell?
yes.. if you design is latch based then you can implement the LSSD style scan instead of mux-scan.
What are lockup latches Why do we use them?
A lock up latch is a sequential circuit which is used to address skew problems when multiple clock domains are used in a chip. From a DFT perspective it holds the previous scan data, and delays output transition so that the scan data can be effectively captured.
What is sequential depth?
sequential depth is the number of capture cycles executed before unloading your scan chains.
Which one is better having single or multiple scan clock?
For the scan chain to shift properly, all scan elements in a given scan chain must have the same scan clock. Multiple clocks may be used if they are made to appear as a single clock.
In which path we insert the lockup latch data or clock path?
The hold check between lockup latch and domain2 flop is already relaxed as it is half cycle check. So, we can say that the correct way to insert a lockup latch is to insert it closer to launching flop and connect the launch domain clock to its clock pin.
What are retiming flops in VLSI?
Retiming of a synchronous sequential circuit is a transformation that moves flip-flops through combinational logic without altering the function. We move the destination flip-flop of a critical path backward through its scan multiplexer. This splits the flip-flop into three, one on each input of the multiplexer.
What is the difference between a latch and a flip-flop?
The major difference between flip-flop and latch is that the flip-flop is an edge-triggered type of memory circuit while the latch is a level-triggered type. It means that the output of a latch changes whenever the input changes.
What is fault grading in DFT?
Fault grading is a procedure that rates testability by relating the number of fabrication defects that can in fact be detected with a test vector set under consideration to the total number of conceivable faults.
What is named capture procedure in DFT?
Named capture procedures provide a simple behavioral model of the clock generation logic. The model describes the behavior of the output clock signal (elk-out) in response to primary input signals (scan-en, scan-clk).
Can a design have multiple clocks?
In the modern ASIC or SOCs the design can have multiple clock sources of different frequencies. For example, consider Fig. 13.1, in this example the flip-flop regA is triggered by CLK1 and flip-flop regB is triggered by CLK2.
What is the function of lock up Latch in DFT?
From a DFT perspective it holds the previous scan data, and delays output transition so that the scan data can be effectively captured. Basically. lock up latch helps prevent problems like clock signal reaching a register too early or later than its intended time.
Which latch or Flop to use as a lockup element?
Either of the latch or flop can be used as a lockup element. This paper covers all such lockup scenarios with latch and register elements and discusses their merits and de-merits.
What is the lock-up latch on the scan path?
Lock-up latches on the scan path act as “break points” across which flops cannot be reordered. Due to lock-up latch on scan path, tool is not able to improve the chain length by reordering in an efficient manner. Whenever there is a lock-up latch in the chain, the scan chain is broken into two smaller segments.
How to add a lock-up Latch to a flip-flop?
Insert the buffers, to add sufficient delay, so that hold timing is finally met. Add the Lock-Up Latch between the two flip-flops where scan chain crosses the functional domains. The first might not be a robust solution because the delay of the buffers would vary across the PVT corners and RC corners.